1. Field of the Invention
This invention relates generally to charge transfer devices and specifically to a charge coupled device suitable for use, for example, in a solid state imager device.
2. Description of the Prior Art
A conventional charge transfer device is a charge coupled device (CCD). Such a device is shown in FIGS. 1 and 2 which illustrate a main portion thereof.
In these drawings, reference numeral 1 designates a P-type silicon substrate which is provided with an input section (not shown), a charge transfer section 2 for transferring signal charges delivered by the input section and a charge detecting section 3 for detecting the signal charges transferred through the charge transfer section 2. Although the input section is not shown in the drawings, it is assumed to be constructed in a known manner such that the signal charges can be delivered to the charge transfer section 2.
The charge transfer section 2 is arranged so as to transfer the signal charges by the use of symmetrical two-phase clock pulses .0..sub.1 and .0..sub.2. More specifically, as a part of the CCD shown in FIGS. 1 and 2, there are formed on the P-type silicon substrate 1 a transfer gate region 4T formed of an N.sup.- -type region, a storage gate region 4S formed of an N-type region, a transfer gate region 5T formed of an N.sup.- -type region and a storage gate region 5S formed of an N-type region which serves as a transfer path for the signal charges. These transfer gate regions are formed sequentially in this order. Furthermore, above the transfer gate region 4T, the storage gate region 4S, the transfer gate region 5T and the storage gate region 5S there are provided, within an insulating layer 6, a transfer gate electrode 7T, a storage gate electrode 7S, a transfer gate electrode 8T and a storage gate electrode 8S, all of which are made of polysilicon and serve as transfer electrodes. The transfer gate electrode 7T and the storage gate electrode 7S are coupled together to a clock pulse input terminal g which is supplied with the clock pulse .0..sub.1. The transfer gate electrode 8T and the storage gate electrode 8S are coupled together to a clock pulse input terminal 10 which is supplied with the other clock pulse .0..sub.2.
The charge detecting section 3 is constructed in a manner such that the signal charges transferred by way of the charge transfer section 2 can be detected undestructively. In the device of FIGS. 1 and 2, a floating gate region 11 of an N-type region is coupled through an output gate region 12 of an N-type region to the storage gate region 5S, which is the terminal portion of the transfer path of the charge transfer section 2. Furthermore, a floating gate electrode 13 and an output gate electrode 14, both made of polysilicon, are provided above the floating gate region 11 and the output gate region 12, respectively, within the insulating layer 6. The output gate electrode 14 is connected to a direct current DC input terminal 15 which is supplied with a predetermined DC voltage V.sub.OG1. The floating gate electrode 13 is connected to an output terminal 17 through an amplifier 16 formed of an MOS-type field effect transistor (MOSFET) formed on the same substrate 1. The floating gate electrode 13 is also connected, through a source drain path of the MOSFET 18 which is triggered by a reset pulse o.sub.RS at its gate electrode, to a DC voltage input terminal 19 which is supplied with a predetermined DC voltage V.sub.RS for reset purposes as is known in the art.
A precharge drain N.sup.+ -type region 20 is formed on the substrate 1 and is coupled to the floating gate region 11 through precharge gate regions 21 and 22 which are formed of N.sup.- -type and N-type regions, respectively. On the precharge drain region 20 there is provided through openings 6A, 6B, 6C and 6D of the insulating layer 6, a precharge drain electrode 23 made of aluminum which is connected to the precharge drain region 20. Above the precharge gate regions 21 and 22, precharge gate electrodes 24 and 25 made of polysilicon are provided within the insulating layer 6 as shown in FIG. 2. The precharge drain electrode 23 is connected to a DC voltage input terminal 26 which is supplied with a predetermined DC voltage V.sub.PD. The precharge gate electrodes 24 and 25 are both connected to a clock pulse input terminal 27 which is supplied with a predetermined clock pulse .0..sub.PG which is synchronized with the clock pulses .0..sub.1 and .0..sub.2.
Additionally, in FIG. 1, reference numeral 28 designates an element isolating region made of selective oxide layer, and reference numerals 29 and 30, designate channel stopper regions indicated by hatchings of broken lines formed of P.sup.+ -type regions.
In the prior art CCD of the present example, the signal charges delivered from the input section are transferred through the transfer paths 4T, 4S, 5T, 5S, . . . . 4T, 4S, 5T, 5S to the floating gate region 11 through the output gate region 12. Thereafter, the signal charges are discharged to the precharge drain region 20 through the precharge gate regions 21 and 22.
When the signal charges are transferred to the floating gate region 11, the electro-static capacity between the floating gate electrode 13 and the substrate 1 is changed. Therefore, the floating gate electrode 13 is always charged with the voltage V.sub.RS through the MOSFET 18 before the signal charges are delivered to the floating gate region 11 so that the voltage change produced in the floating gate electrode 13 corresponds to the amount of the transferred signal charges to the floating gate region 11. Thus, the CCD of the present example can provide at the output terminal 17 an amplified signal representative of the change in voltage produced in the floating gate electrode 13 corresponding to the amount of the transferred signal charges as an output signal.
As shown further in FIGS. 1 and 2, the rear end portion of the output gate electrode 14 and the front end portion of the floating gate electrode 13 overlap each other within the insulating layer 6, and the rear end portion of the floating gate electrode 13 and the front end portion of the precharge gate electrode 24 overlap each other within the insulating layer 6, so as to prevent potential barriers between the output gate region 12 and the floating gate region 11 and between the floating gate region 11 and the precharge gate region 21, respectively, so that the signal charges can be transferred smoothly.
However, in the above described CCD, the area of overlap of portion 31 of the floating gate electrode 13 and the output gate electrode 14, the area of overlap of portion 32 of the floating gate electrode 13 and the precharge gate electrode 24 and the area of overlap of portions 33 and 34 of the floating gate electrode 13 and the channel stopper regions 29 and 30 are relatively wide. Therefore, the parasitic capacitance of the floating gate electrode 13 becomes large enough so that the charge detecting sensitivity at the floating gate electrode 13 is decreased. In other words, the charge voltage converting gain at the floating gate electrode 13 is decreased and accordingly an output signal with a good signal/noise ratio cannot be provided at the output terminal 17.
With the recent tendency in the art of aiming for a highly dense and integrated solid state imager device, the light receiving area has been decreasing so that the amount of the signal charges treated in one pixcel has become less and less. Therefore, there has been strongly desired, a CCD for use in such solid state imager devices to provide an output signal with a good signal/noise ratio despite the decrease in light receiving areas.